1. Field of the Invention
Apparatuses and methods consistent with the present invention relate to operating a flash memory according to a priority order, and more particularly, to operating a flash memory according to a priority order, which ensures fast response time.
2. Description of the Related Art
Generally, embedded systems, such as electric home appliances, communication devices, and set top boxes, widely employ a nonvolatile memory as a storage medium that stores and processes data.
A flash memory, which is mainly used as the nonvolatile memory, is a memory device that can electrically erase or rewrite data. Such a flash memory is suitable for a portable device owing to its lower power consumption than a storage medium based on a magnetic disk memory, its fast access time equal to that of a hard disk, and its small size.
Also, the flash memory basically has write, read and erase operations and has hardware characteristics which require an erase operation of erasing a block before writing data. The erase operation of the flash memory takes long time when compared to a write operation and a read operation. Also, in case of operations of erasing several blocks simultaneously or reading/writing several pages at a time, the operations take longer time.
A real-time system which uses the flash memory has operations in various priority orders. If an operation having a high priority is requested, an operation having a low priority is suspended and the operation having a high priority is performed. If operations are requested to the system, the requested operations are arrayed according to priority order in an operation queue and are performed in the flash memory, by transferring information necessary for the flash order and execution to the flash memory through a flash translation layer before the operation in the operation queue is performed.
If, while an operation is in progress, an operation having a higher priority than the currently performed operation is requested, the flash memory usually operates the requested operation after finishing the currently performed operation.
At this time, in the system which uses a flash memory and requires a real-time response, even if an operation having a higher priority is requested during execution of a certain operation, since the operation having a higher priority is put on the standby until the current operation is completed, the system has a long response time.
Specifically, as shown in FIG. 1, when an operation having a high priority is requested during the execution of a certain operation, the requested operation is performed after being in a standby state until the currently performed operation is completed. However, it causes a delay of the response time in the real-time system.
Thus, in order to avoid the delay of the response time in the real-time system, if an operation having a high priority is requested while a certain operation is performed, the currently performed operation is suspended, and then is resumed and completed after the operation having a high priority is performed, thereby improving the response time. At this time, the operation suspension time for suspending the operation is required, and the operation resumption time for resuming the operation is also required.
However, as shown in FIG. 2, when an operation having a high priority is requested during the execution of a certain operation, if the currently performed operation is unconditionally suspended, the remaining time until completion of the currently performed operation is not considered. Thus, if the operation suspension time necessary for suspending the currently performed operation is more than the remaining time until completion of the currently performed operation, a problem occurs in that performing the operation having a high priority after the completion of the currently performed operation has a faster response time.
Also, if the currently performed operation is an erase operation, since the erase operation is suspended and then resumed after the execution of the operation having a high priority, a problem occurs in that the number of erase operations affecting the lifetime reduction of the flash memory is increased.
Japanese Patent Unexamined Publication No. 1998-177563 discloses a built-in microcomputer which stops providing the clock from a clock generation means to a CPU, according to signals output from a control circuit during a write period or an erase period to the flash memory.
However, this related art is to prevent the overload arisen from the frequent polling of the CPU on the completion of the write/erase operation of a flash memory while the write/erase operation of the flash memory is performed. That is, this related art fails to disclose a method of reducing the response time when an operation having a high priority is requested during the execution of a certain operation, in a real-time system which uses the flash memory.